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Cadence SP&R Used by Sunplus to Design One-million-gate Chip
SAN JOSE, Calif.--(BUSINESS WIRE)--Aug. 27, 2001--Cadence Design
Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic
design products and services, today announced that Sunplus, a leading
chip design company in Taiwan for advanced consumer electronic
systems, has designed and taped-out its first chip for use in a
high-performance MPEG2 video decoder using the Cadence® SP&R
(synthesis/place-and-route) design flow. Using Cadence Physically
Knowledgeable Synthesis (PKS) physical synthesis and Silicon
Ensemble(TM) PKS (SE-PKS) optimization place-and-route tools, Sunplus
achieved its time-to-market goals with one-pass timing closure on its
new one-million-gate chip.
``To meet the fast-moving technology demands driven by dynamic
consumer electronic systems, we have been looking for a robust design
solution to control iteration and chip performance,'' said Ching-Hsiang
Yang, manager of the CAD Department at Sunplus. ``In searching for a
perfect physical synthesis tool to produce high performance systems
with the least turn-around time and lowest cost, Cadence PKS proved to
be the best solution for achieving one-pass timing closure. The highly
integrated PKS provided excellent quality because of its integrated
clock, and its placement and global routing technologies.''
Sunplus develops higher-performance devices for customers in the
audio/video consumer and PC peripheral electronic products markets.
Before implementing the complete SP&R flow for production designs in
0.25-micron technology and below, Sunplus evaluated Cadence PKS by
re-characterizing several in-house projects. PKS outperformed previous
results on each project, achieving timing closure in one-pass flow on
most projects. PKS achieved pre- and post-route timing closure of less
than 0.5 nanoseconds on the 81 MHz production design, despite the
complexity of a high gate-count, more than 40 various functional
blocks, and critical clock specifications.
``We are pleased that Sunplus chose to integrate the Cadence SP&R
flow in its next-generation SOC implementation methodology,'' said
Matthew Chan, president, Cadence Asia Pacific. ``Our SP&R solutions
enable customers like Sunplus to develop chips quickly. They do this
by significantly reducing iterations using our superior methodology
for addressing timing closure, while achieving excellent performance.''
About Cadence SP&R
Cadence SP&R is the industry's first unified
synthesis/place-and-route system. It consists of PKS physical
synthesis and Silicon Ensemble PKS (SE-PKS) optimization
place-and-route. SP&R features correlation within three percent
through common timing, synthesis, placement, and routing engines used
by both logic designers and physical designers.
About Cadence PKS Physical Synthesis
Cadence PKS is the most complete and tightly integrated physical
synthesis offering available today. It achieves tight correlation with
final routed results because its synthesis, timing, and placement, and
true global routing engines are integrated into the same tool. This
integration also provides better quality-of-results, seen in the
frequency and area of the design.
About Silicon Ensemble PKS Optimization Place-and-Route
Silicon Ensemble PKS (SE-PKS) uses Cadence PKS technology to
completely restructure gate-level netlists produced by conventional
wireload-model-based synthesis. It can also directly read PKS
databases that contain placement and global routing information,
making it the only place-and-route tool that can accept
forward-annotated global routing. SE-PKS is a comprehensive
place-and-route tool that incorporates enhanced industry-standard
constraint support, which makes it much easier to move designs from
conventional synthesis into place-and-route, and to adopt a
timing-driven design flow.
Pricing and Availability
Cadence PKS physical synthesis and SE-PKS optimization
place-and-route are available for UNIX-based workstations from
Hewlett-Packard and Sun Microsystems, and for AIX-based workstations
from IBM. One-year U.S. list prices start at $100,000 and $400,000,
respectively. For information on international pricing, please contact
the local Cadence sales office.
About Sunplus
Founded in 1990, Sunplus is the number one consumer chip design
house in Taiwan and was the 19th fabless design house worldwide in
2000. The company had been working with worldwide leading companies in
consumer and computer business to provide them the best cost-
performance IC solutions. With 390 employees, there were more than one
thousand different products and 465 million chips shipped to the
customers and the revenue was $193 million in 2000. The company is
headquartered in Science Park, Hsinchu, and traded on the Taiwan Stock
Exchange under the symbol 2401. More information about the company,
its products, and its services may be obtained from the World Wide Web
at http://www.sunplus.com.tw (or http://www.maxfun.com).
About Cadence
Cadence is the largest supplier of electronic design automation
products, methodology services, and design services. Cadence solutions
are used to accelerate and manage the design of semiconductors,
computer systems, networking and telecommunications equipment,
consumer electronics, and a variety of other electronics-based
products. With approximately 5,700 employees and 2000 revenues of
approximately $1.3 billion, Cadence has sales offices, design centers,
and research facilities around the world. The company is headquartered
in San Jose, Calif., and traded on the New York Stock Exchange under
the symbol CDN. More information about the company, its products, and
services is available at www.cadence.com.
Note to Editors: Cadence and the Cadence logo are registered
trademarks, and Silicon Ensemble is a trademark of Cadence Design
Systems, Inc. All other trademarks are the property of their
respective owners.
Contact:
Cadence Design Systems, Inc.
Parvesh Bal-Sandhu, 408/894-2512
parvesh@cadence.com
or
Cadence Design Systems, Inc., Taiwan
Hsin-Kai Lee, 886-2-8761-1129
hkl@cadence.com
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